Computers and other modem processing systems have revolutionized the electronics industry by enabling sophisticated tasks to be performed with a few strokes of a keypad. These sophisticated tasks often involve a number of devices that communicate with one another in a fast and efficient manner using a bus. The bus provides a shared communication link between devices in a processing system.
The types of devices connected to a bus in a processing system may vary depending on the particular application. Commonly, the bus is configured to support a number of processors, memory devices, and peripherals. In these systems, the processors often achieve performance benefits by allowing memory operations to be performed out-of-order. For example, a processing system may achieve performance benefits by reordering a sequence of memory operations to allow all operations to the same page in memory to be executed before a new page is opened. Processing systems that are allowed to reorder memory operations are generally referred to as “weakly-ordered” processing systems.
In certain instances, the reordering of memory operations may unpredictably affect program behavior. For instance, an application may require a processor to write data to memory before the processor reads from memory. In a weakly-ordered processing system, there is no guarantee that this will occur. This result may be unacceptable.
Various techniques have been employed for executing ordered memory operations in a weakly-ordered processing system. One technique is simply to delay certain memory operations until all memory operations before it are executed. In the previous example, the processor may delay issuing a read request until it receives an indication that guarantees that the data has been written to the memory.
A common technique in modern day processor architectures is to use a bus command known as a “memory barrier” when an ordered memory operation is required. A “memory barrier” may be used to ensure that all memory access requests issued by a processor before the memory barrier are executed before all memory access requests issued by the processor after the memory barrier. Again, in the previous example, a memory barrier could be sent to the memory by the processor before issuing a read request. This would ensure that the processor writes to memory before it reads from the memory.
Memory barriers are an effective way to impose ordering constraints on memory operations in weakly-ordered processing systems, but are inefficient from a system performance perspective. The memory barrier may be particularly inefficient in processing systems with multiple memory devices. In these processing systems, a memory barrier would need to be issued by the processor to every memory device it can access to enforce an ordering constraint on memory operations. As a result, the next memory operation following a memory barrier is delayed until each memory device accessible by the processor completes all outstanding memory operations. Thus, there is a continuing need for more efficient methods to perform memory barrier operations in a weakly-ordered processing system.